A - Accumulator SP - Stack Pointer I - Interrupt Vector Register IM 1 - interrupt mode 1 R - Memory Refresh Register IX,IY - Index Registers F3 (B) - DI ;Resetting the interrupt enable flip-flops (IFF1 and IFF2) (IFF1 and IFF2). FB (B) - EI ;allowing recognition of any maskable interrupt. 10 + $Displacement (B+B) - DJNZ B on $ ;the same that dbra in M68K 18 + $Displacement (B+B) - JR PC on $ 20 + $Displacement (B+B) - JR NZ PC on $ 28 + $Displacement (B+B) - JR Z on $ ;if Z=1 then displ. 30 + $Displacement (B+B) - JR NC PC on $ 38 + $Displacement (B+B) - JR C PC on $ C3 Address (B+W) - JP Address E9 (B) - JP (HL) DDE9 (W) - JP (IX) C2 + Address (B+W) - JP if NZ non zero then to Address CA + Address (B+W) - JP if Z zero then to Address D2 + Address (B+W) - JP if NC no carry then to Address DA + Address (B+W) - JP if C carry then to Address E2 + Address (B+W) - JP if PO parity odd then to Address EA + Address (B+W) - JP if PE parity even then to Address F2 + Address (B+W) - JP if P sign positive then to Address FA + Address (B+W) - JP if M sign negative then to Address 00 (B) - NOP C9 (B) - RET C0 (B) - RET NZ ;non zero C8 (B) - RET Z ;zero D0 (B) - RET NC ;non carry D8 (B) - RET C ;carry E0 (B) - RET PO ;parity odd E8 (B) - RET PE ;parity even F0 (B) - RET P ;sign positive F8 (B) - RET M ;sign negative CD + Address (B+W) - CALL Address C4 + Address (B+W) - CALL NZ Address ;non zero CC + Address (B+W) - CALL Z Address ;zero D4 + Address (B+W) - CALL NC Address ;non carry DC + Address (B+W) - CALL C Address ;carry E4 + Address (B+W) - CALL PO Address ;parity odd EC + Address (B+W) - CALL PE Address ;parity even F4 + Address (B+W) - CALL P Address ;sign positive FC + Address (B+W) - CALL M Address ;sign negative ED45 (W) - RETN ED4D (W) - RETI ED46 (W) - IM 0; In this mode, the interrupting device can insert any instruction on the data bus for execution by the CPU ED56 (W) - IM 1 ;In this mode, the processor responds to an interrupt by executing a restart to location 0038H ED5F (W) - LD R to A EDB0 (W) - LDIR (HL)+ to (DE)+ ;if BC not Zero then BC-1 F5 (B) - PUSH AF ;pair qq are pushed to the external memory LIFO (last-in, first-out) Stack C5 (B) - PUSH BC ;pair qq are pushed to the external memory LIFO (last-in, first-out) Stack D5 (B) - PUSH DE ;pair qq are pushed to the external memory LIFO (last-in, first-out) Stack E5 (B) - PUSH HL ;pair qq are pushed to the external memory LIFO (last-in, first-out) Stack FDE5 (W) - PUSH IY DDE5 (W) - PUSH IX FD23 (W) - INC IY DD23 (W) - INC IX DB Address (B+B) - IN Address ;Select I/O Port through half address A0-A7 D3 Address (B+B) - OUT Address ;Select I/O Port through half address A0-A7 ED41 (W) - OUT B to (C) ;Select I/O Port through half address A0-A7 ED49 (W) - OUT C to (C) ;Select I/O Port through half address A0-A7 ED51 (W) - OUT D to (C) ;Select I/O Port through half address A0-A7 ED59 (W) - OUT E to (C) ;Select I/O Port through half address A0-A7 ED61 (W) - OUT H to (C) ;Select I/O Port through half address A0-A7 ED69 (W) - OUT L to (C) ;Select I/O Port through half address A0-A7 ED79 (W) - OUT A to (C) ;Select I/O Port through half address A0-A7 EDA3 (W) - OUTI B8 (B) - CP B ;compared with the contents of the A, if there is a true compare, the Z flag is set B9 (B) - CP C ;compared with the contents of the A, if there is a true compare, the Z flag is set BA (B) - CP D ;compared with the contents of the A, if there is a true compare, the Z flag is set BB (B) - CP E ;compared with the contents of the A, if there is a true compare, the Z flag is set BC (B) - CP H ;compared with the contents of the A, if there is a true compare, the Z flag is set BD (B) - CP L ;compared with the contents of the A, if there is a true compare, the Z flag is set BF (B) - CP A ;compared with the contents of the A, if there is a true compare, the Z flag is set BE (B) - CP (HL) FE + $DATA (B+B) - CP $ DDBE + $Displacement (W+B) - CP A with IX + $ FDBE + $Displacement (W+B) - CP A with IY + $ EDA1 (W) - CPI (HL) with A 40 (B) - LD B to B 41 (B) - LD C to B 42 (B) - LD D to B 43 (B) - LD E to B 44 (B) - LD H to B 45 (B) - LD L to B 47 (B) - LD A to B 48 (B) - LD B to C 49 (B) - LD C to C 4A (B) - LD D to C 4B (B) - LD E to C 4C (B) - LD H to C 4D (B) - LD L to C 4F (B) - LD A to C 50 (B) - LD B to D 51 (B) - LD C to D 52 (B) - LD D to D 53 (B) - LD E to D 54 (B) - LD H to D 55 (B) - LD L to D 57 (B) - LD A to D 58 (B) - LD B to E 59 (B) - LD C to E 5A (B) - LD D to E 5B (B) - LD E to E 5C (B) - LD H to E 5D (B) - LD L to E 5F (B) - LD A to E 60 (B) - LD B to H 61 (B) - LD C to H 62 (B) - LD D to H 63 (B) - LD E to H 64 (B) - LD H to H 65 (B) - LD L to H 67 (B) - LD A to H 68 (B) - LD B to L 69 (B) - LD C to L 6A (B) - LD D to L 6B (B) - LD E to L 6C (B) - LD H to L 6D (B) - LD L to L 6F (B) - LD A to L 78 (B) - LD B to A 79 (B) - LD C to A 7A (B) - LD D to A 7B (B) - LD E to A 7C (B) - LD H to A 7D (B) - LD L to A 7F (B) - LD A to A 70 (B) - LD B to (HL) 71 (B) - LD C to (HL) 72 (B) - LD D to (HL) 73 (B) - LD E to (HL) 74 (B) - LD H to (HL) 75 (B) - LD L to (HL) 77 (B) - LD A to (HL) 46 (B) - LD (HL) to B 4E (B) - LD (HL) to C 56 (B) - LD (HL) to D 5E (B) - LD (HL) to E 66 (B) - LD (HL) to H 6E (B) - LD (HL) to L 7E (B) - LD (HL) to A 02 (B) - LD A to (BC) 0A (B) - LD (BC) to A 12 (B) - LD A to (DE) 1A (B) - LD (DE) to A 3A + Address (B+W) - LD Address to A 32 + Address (B+W) - LD A to Address 36 + $DATA (B+B) - LD $ to (HL) ;to memory address in HL 22 + Address (B+W) - LD L to Address, H to Addr+1 2A + Address (B+W) - LD Address to L, Addr+1 to H 06 + $DATA (B+B) - LD $ to B 0E + $DATA (B+B) - LD $ to C 16 + $DATA (B+B) - LD $ to D 1E + $DATA (B+B) - LD $ to E 26 + $DATA (B+B) - LD $ to H 2E + $DATA (B+B) - LD $ to L 3E + $DATA (B+B) - LD $ to A 01 + $DATA (B+W) - LD $ to BC 11 + $DATA (B+W) - LD $ to DE 21 + $DATA (B+W) - LD $ to HL 31 + $DATA (B+W) - LD $ to SP ED57 (W) - LD I to A ED47 (W) - LD A to I ED43 + Address (W+W) - LD C to Address, B to Addr+1 ED53 + Address (W+W) - LD E to Address, D to Addr+1 ED63 + Address (W+W) - LD L to Address, H to Addr+1 ED73 + Address (W+W) - LD P to Address, S to Addr+1 ED4B + Address (W+W) - LD Address to C, Addr+1 to B ED5B + Address (W+W) - LD Address to E, Addr+1 to D ED6B + Address (W+W) - LD Address to L, Addr+1 to H ED7B + Address (W+W) - LD Address to P, Addr+1 to S FD21 + $DATA (W+W) - LD $ to IY DD21 + $DATA (W+W) - LD $ to IX FD70 + $DATA (W+B) - LD B to IY + $ FD71 + $DATA (W+B) - LD C to IY + $ FD72 + $DATA (W+B) - LD D to IY + $ FD73 + $DATA (W+B) - LD E to IY + $ FD74 + $DATA (W+B) - LD H to IY + $ FD75 + $DATA (W+B) - LD L to IY + $ FD77 + $DATA (W+B) - LD A to IY + $ DD70 + $DATA (W+B) - LD B to IX + $ DD71 + $DATA (W+B) - LD C to IX + $ DD72 + $DATA (W+B) - LD D to IX + $ DD73 + $DATA (W+B) - LD E to IX + $ DD74 + $DATA (W+B) - LD H to IX + $ DD75 + $DATA (W+B) - LD L to IX + $ DD77 + $DATA (W+B) - LD A to IX + $ FD36 + $Displacement + $DATA (W+B+B) - LD $ to IY + $ DD36 + $Displacement + $DATA (W+B+B) - LD $ to IX + $ FD46 + $Displacement (W+B) - LD IY + $ to B FD4E + $Displacement (W+B) - LD IY + $ to C FD56 + $Displacement (W+B) - LD IY + $ to D FD5E + $Displacement (W+B) - LD IY + $ to E FD66 + $Displacement (W+B) - LD IY + $ to H FD6E + $Displacement (W+B) - LD IY + $ to L FD7E + $Displacement (W+B) - LD IY + $ to A DD46 + $Displacement (W+B) - LD IX + $ to B DD4E + $Displacement (W+B) - LD IX + $ to C DD56 + $Displacement (W+B) - LD IX + $ to D DD5E + $Displacement (W+B) - LD IX + $ to E DD66 + $Displacement (W+B) - LD IX + $ to H DD6E + $Displacement (W+B) - LD IX + $ to L DD7E + $Displacement (W+B) - LD IX + $ to A DDE1 (W) - POP IX FDE1 (W) - POP IY B0 (B) - OR B to A B1 (B) - OR C to A B2 (B) - OR D to A B3 (B) - OR E to A B4 (B) - OR H to A B5 (B) - OR L to A B7 (B) - OR A to A B6 (B) - OR (HL) to A F6 + $DATA (B+B) - OR $ to A DDB6 + $Displacement (W+B) - OR (IX + $) to A A0 (B) - AND B to A A1 (B) - AND C to A A2 (B) - AND D to A A3 (B) - AND E to A A4 (B) - AND H to A A5 (B) - AND L to A A7 (B) - AND A to A A6 (B) - AND (HL) to A E6 + $DATA (B+B) - AND $ to A C6 + $DATA (B+B) - ADD $ to A DDA6 + $Displacement (W+B) - AND (IX + $) to A 86 (B) - ADD (HL) to A 80 (B) - ADD B to A 81 (B) - ADD C to A 82 (B) - ADD D to A 83 (B) - ADD E to A 84 (B) - ADD H to A 85 (B) - ADD L to A 87 (B) - ADD A to A 09 (B) - ADD BC to HL 19 (B) - ADD DE to HL 29 (B) - ADD HL to HL 39 (B) - ADD SP to HL FD09 (W) - ADD BC to IY FD19 (W) - ADD DE to IY FD29 (W) - ADD IY to IY FD39 (W) - ADD SP to IY DD09 (W) - ADD BC to IX DD19 (W) - ADD DE to IX DD29 (W) - ADD IY to IX DD39 (W) - ADD SP to IX FD86 + $Displacement (W+B) - ADD (IY + $) to A DD86 + $Displacement (W+B) - ADD (IX + $) to A 90 (B) - SUB B to A 91 (B) - SUB C to A 92 (B) - SUB D to A 93 (B) - SUB E to A 94 (B) - SUB H to A 95 (B) - SUB L to A 97 (B) - SUB A to A D6 + $DATA (B+B) - SUB $ to A DD96 + $Displacement (W+B) - SUB (IX + $) to A 04 (B) - INC B 0C (B) - INC C 14 (B) - INC D 1C (B) - INC E 24 (B) - INC H 2C (B) - INC L 3C (B) - INC A 03 (B) - INC BC 13 (B) - INC DE 23 (B) - INC HL 33 (B) - INC SP 34 (B) - INC (HL) 05 (B) - DEC B 0D (B) - DEC C 15 (B) - DEC D 1D (B) - DEC E 25 (B) - DEC H 2D (B) - DEC L 3D (B) - DEC A 0B (B) - DEC BC 1B (B) - DEC DE 2B (B) - DEC HL 3B (B) - DEC SP 35 (B) - DEC (HL) FD35 + $Displacement (W+B) - DEC (IY + $) DD35 + $Displacement (W+B) - DEC (IX + $) C1 (B) - POP SP to BC D1 (B) - POP SP to DE E1 (B) - POP SP to HL F1 (B) - POP SP to AF 08 (B) - EX AF ;2 bytes AF are exchanged EB (B) - EX DE, HL ;2 bytes AF are exchanged DDE3 (W) - EX (SP), IX ED42 (W) - SBC BC to HL ED52 (W) - SBC DE to HL ED62 (W) - SBC HL to HL ED72 (W) - SBC SP to HL 07 (B) - RLCA ;the same that ROL in M68K 0F (B) - RRCA ;the same that ROR in M68K 17 (B) - RLA 1F (B) - RRA AC (B) - XOR H to A AF (B) - XOR A to A ;Clear Accumulator in fact EE + $DATA (B+B) - XOR $ to A 37 (B) - SCF ;the Carry flag in the F register is set 3F (B) - CCF ;The Carry flag in the F register is inverted D9 (B) - EXX CB18 (W) - RR B ;content of register are rotated right 1-bit position through the Carry flag CB19 (W) - RR C ;content of register are rotated right 1-bit position through the Carry flag CB1A (W) - RR D ;content of register are rotated right 1-bit position through the Carry flag CB1B (W) - RR E ;content of register are rotated right 1-bit position through the Carry flag CB1C (W) - RR H ;content of register are rotated right 1-bit position through the Carry flag CB1D (W) - RR L ;content of register are rotated right 1-bit position through the Carry flag CB1F (W) - RR A ;content of register are rotated right 1-bit position through the Carry flag CB00 (W) - RLC B ;the same that ROL in M68K CB01 (W) - RLC C ;the same that ROL in M68K CB02 (W) - RLC D ;the same that ROL in M68K CB03 (W) - RLC E ;the same that ROL in M68K CB04 (W) - RLC H ;the same that ROL in M68K CB05 (W) - RLC L ;the same that ROL in M68K CB07 (W) - RLC A ;the same that ROL in M68K CB20 (W) - SLA B ;Shift left 1-bit position CB21 (W) - SLA C ;Shift left 1-bit position CB22 (W) - SLA D ;Shift left 1-bit position CB23 (W) - SLA E ;Shift left 1-bit position CB24 (W) - SLA H ;Shift left 1-bit position CB25 (W) - SLA L ;Shift left 1-bit position CB27 (W) - SLA A ;Shift left 1-bit position CB28 (W) - SRA B ;Shift right 1-bit position CB29 (W) - SRA C ;Shift right 1-bit position CB2A (W) - SRA D ;Shift right 1-bit position CB2B (W) - SRA E ;Shift right 1-bit position CB2C (W) - SRA H ;Shift right 1-bit position CB2D (W) - SRA L ;Shift right 1-bit position CB2F (W) - SRA A ;Shift right 1-bit position CB38 (W) - SRL B ;Shift right 1-bit position CB39 (W) - SRL C ;Shift right 1-bit position CB3A (W) - SRL D ;Shift right 1-bit position CB3B (W) - SRL E ;Shift right 1-bit position CB3C (W) - SRL H ;Shift right 1-bit position CB3D (W) - SRL L ;Shift right 1-bit position CB3F (W) - SRL A ;Shift right 1-bit position CBC0 (W) - SET bit 8 to B CBC1 (W) - SET bit 8 to C CBC2 (W) - SET bit 8 to D CBC3 (W) - SET bit 8 to E CBC4 (W) - SET bit 8 to H CBC5 (W) - SET bit 8 to L CBC7 (W) - SET bit 8 to A CBC8 (W) - SET bit 1 to B CBC9 (W) - SET bit 1 to C CBCA (W) - SET bit 1 to D CBCB (W) - SET bit 1 to E CBCC (W) - SET bit 1 to H CBCD (W) - SET bit 1 to L CBCF (W) - SET bit 1 to A CBD0 (W) - SET bit 2 to B CBD1 (W) - SET bit 2 to C CBD2 (W) - SET bit 2 to D CBD3 (W) - SET bit 2 to E CBD4 (W) - SET bit 2 to H CBD5 (W) - SET bit 2 to L CBD7 (W) - SET bit 2 to A CBD8 (W) - SET bit 3 to B CBD9 (W) - SET bit 3 to C CBDA (W) - SET bit 3 to D CBDB (W) - SET bit 3 to E CBDC (W) - SET bit 3 to H CBDD (W) - SET bit 3 to L CBDF (W) - SET bit 3 to A CBE0 (W) - SET bit 4 to B CBE1 (W) - SET bit 4 to C CBE2 (W) - SET bit 4 to D CBE3 (W) - SET bit 4 to E CBE4 (W) - SET bit 4 to H CBE5 (W) - SET bit 4 to L CBE7 (W) - SET bit 4 to A CBE8 (W) - SET bit 5 to B CBE9 (W) - SET bit 5 to C CBEA (W) - SET bit 5 to D CBEB (W) - SET bit 5 to E CBEC (W) - SET bit 5 to H CBED (W) - SET bit 5 to L CBEF (W) - SET bit 5 to A CBF0 (W) - SET bit 6 to B CBF1 (W) - SET bit 6 to C CBF2 (W) - SET bit 6 to D CBF3 (W) - SET bit 6 to E CBF4 (W) - SET bit 6 to H CBF5 (W) - SET bit 6 to L CBF7 (W) - SET bit 6 to A CBF8 (W) - SET bit 7 to B CBF9 (W) - SET bit 7 to C CBFA (W) - SET bit 7 to D CBFB (W) - SET bit 7 to E CBFC (W) - SET bit 7 to H CBFD (W) - SET bit 7 to L CBFF (W) - SET bit 7 to A FDCB + $Displacement + CE (W+B+B) - SET bit 1 to (IY + $) FDCB + $Displacement + D6 (W+B+B) - SET bit 2 to (IY + $) FDCB + $Displacement + DE (W+B+B) - SET bit 3 to (IY + $) FDCB + $Displacement + E6 (W+B+B) - SET bit 4 to (IY + $) FDCB + $Displacement + EE (W+B+B) - SET bit 5 to (IY + $) FDCB + $Displacement + F6 (W+B+B) - SET bit 6 to (IY + $) FDCB + $Displacement + FE (W+B+B) - SET bit 7 to (IY + $) FDCB + $Displacement + C6 (W+B+B) - SET bit 8 to (IY + $) DDCB + $Displacement + CE (W+B+B) - SET bit 1 to (IX + $) DDCB + $Displacement + D6 (W+B+B) - SET bit 2 to (IX + $) DDCB + $Displacement + DE (W+B+B) - SET bit 3 to (IX + $) DDCB + $Displacement + E6 (W+B+B) - SET bit 4 to (IX + $) DDCB + $Displacement + EE (W+B+B) - SET bit 5 to (IX + $) DDCB + $Displacement + F6 (W+B+B) - SET bit 6 to (IX + $) DDCB + $Displacement + FE (W+B+B) - SET bit 7 to (IX + $) DDCB + $Displacement + C6 (W+B+B) - SET bit 8 to (IX + $) CB80 (W) - RES bit 8 to B CB81 (W) - RES bit 8 to C CB82 (W) - RES bit 8 to D CB83 (W) - RES bit 8 to E CB84 (W) - RES bit 8 to H CB85 (W) - RES bit 8 to L CB87 (W) - RES bit 8 to A CB88 (W) - RES bit 1 to B CB89 (W) - RES bit 1 to C CB8A (W) - RES bit 1 to D CB8B (W) - RES bit 1 to E CB8C (W) - RES bit 1 to H CB8D (W) - RES bit 1 to L CB8F (W) - RES bit 1 to A CB90 (W) - RES bit 2 to B CB91 (W) - RES bit 2 to C CB92 (W) - RES bit 2 to D CB93 (W) - RES bit 2 to E CB94 (W) - RES bit 2 to H CB95 (W) - RES bit 2 to L CB97 (W) - RES bit 2 to A CB98 (W) - RES bit 3 to B CB99 (W) - RES bit 3 to C CB9A (W) - RES bit 3 to D CB9B (W) - RES bit 3 to E CB9C (W) - RES bit 3 to H CB9D (W) - RES bit 3 to L CB9F (W) - RES bit 3 to A CBA0 (W) - RES bit 4 to B CBA1 (W) - RES bit 4 to C CBA2 (W) - RES bit 4 to D CBA3 (W) - RES bit 4 to E CBA4 (W) - RES bit 4 to H CBA5 (W) - RES bit 4 to L CBA7 (W) - RES bit 4 to A CBA8 (W) - RES bit 5 to B CBA9 (W) - RES bit 5 to C CBAA (W) - RES bit 5 to D CBAB (W) - RES bit 5 to E CBAC (W) - RES bit 5 to H CBAD (W) - RES bit 5 to L CBAF (W) - RES bit 5 to A CBB0 (W) - RES bit 6 to B CBB1 (W) - RES bit 6 to C CBB2 (W) - RES bit 6 to D CBB3 (W) - RES bit 6 to E CBB4 (W) - RES bit 6 to H CBB5 (W) - RES bit 6 to L CBB7 (W) - RES bit 6 to A CBB8 (W) - RES bit 7 to B CBB9 (W) - RES bit 7 to C CBBA (W) - RES bit 7 to D CBBB (W) - RES bit 7 to E CBBC (W) - RES bit 7 to H CBBD (W) - RES bit 7 to L CBBF (W) - RES bit 7 to A FDCB + $Displacement + 8E (W+B+B) - RES bit 1 to (IY + $) FDCB + $Displacement + 96 (W+B+B) - RES bit 2 to (IY + $) FDCB + $Displacement + 9E (W+B+B) - RES bit 3 to (IY + $) FDCB + $Displacement + A6 (W+B+B) - RES bit 4 to (IY + $) FDCB + $Displacement + AE (W+B+B) - RES bit 5 to (IY + $) FDCB + $Displacement + B6 (W+B+B) - RES bit 6 to (IY + $) FDCB + $Displacement + BE (W+B+B) - RES bit 7 to (IY + $) FDCB + $Displacement + 86 (W+B+B) - RES bit 8 to (IY + $) DDCB + $Displacement + 8E (W+B+B) - RES bit 1 to (IX + $) DDCB + $Displacement + 96 (W+B+B) - RES bit 2 to (IX + $) DDCB + $Displacement + 9E (W+B+B) - RES bit 3 to (IX + $) DDCB + $Displacement + A6 (W+B+B) - RES bit 4 to (IX + $) DDCB + $Displacement + AE (W+B+B) - RES bit 5 to (IX + $) DDCB + $Displacement + B6 (W+B+B) - RES bit 6 to (IX + $) DDCB + $Displacement + BE (W+B+B) - RES bit 7 to (IX + $) DDCB + $Displacement + 86 (W+B+B) - RES bit 8 to (IX + $) C7 (B) - RST 00H CF (B) - RST 08H D7 (B) - RST 10H DF (B) - RST 18H E7 (B) - RST 20H EF (B) - RST 28H F7 (B) - RST 30H FF (B) - RST 38H CB48 (W) - BIT bit 1 in B CB49 (W) - BIT bit 1 in C CB4A (W) - BIT bit 1 in D CB4B (W) - BIT bit 1 in E CB4C (W) - BIT bit 1 in H CB4D (W) - BIT bit 1 in L CB4F (W) - BIT bit 1 in A CB50 (W) - BIT bit 2 in B CB51 (W) - BIT bit 2 in C CB52 (W) - BIT bit 2 in D CB53 (W) - BIT bit 2 in E CB54 (W) - BIT bit 2 in H CB55 (W) - BIT bit 2 in L CB57 (W) - BIT bit 2 in A CB58 (W) - BIT bit 3 in B CB59 (W) - BIT bit 3 in C CB5A (W) - BIT bit 3 in D CB5B (W) - BIT bit 3 in E CB5C (W) - BIT bit 3 in H CB5D (W) - BIT bit 3 in L CB5F (W) - BIT bit 3 in A CB60 (W) - BIT bit 4 in B CB61 (W) - BIT bit 4 in C CB62 (W) - BIT bit 4 in D CB63 (W) - BIT bit 4 in E CB64 (W) - BIT bit 4 in H CB65 (W) - BIT bit 4 in L CB67 (W) - BIT bit 4 in A CB68 (W) - BIT bit 5 in B CB69 (W) - BIT bit 5 in C CB6A (W) - BIT bit 5 in D CB6B (W) - BIT bit 5 in E CB6C (W) - BIT bit 5 in H CB6D (W) - BIT bit 5 in L CB6F (W) - BIT bit 5 in A CB70 (W) - BIT bit 6 in B CB71 (W) - BIT bit 6 in C CB72 (W) - BIT bit 6 in D CB73 (W) - BIT bit 6 in E CB74 (W) - BIT bit 6 in H CB75 (W) - BIT bit 6 in L CB77 (W) - BIT bit 6 in A CB78 (W) - BIT bit 7 in B CB79 (W) - BIT bit 7 in C CB7A (W) - BIT bit 7 in D CB7B (W) - BIT bit 7 in E CB7C (W) - BIT bit 7 in H CB7D (W) - BIT bit 7 in L CB7F (W) - BIT bit 7 in A CB40 (W) - BIT bit 8 in B CB41 (W) - BIT bit 8 in C CB42 (W) - BIT bit 8 in D CB43 (W) - BIT bit 8 in E CB44 (W) - BIT bit 8 in H CB45 (W) - BIT bit 8 in L CB47 (W) - BIT bit 8 in A CB4E (W) - BIT bit 1 in (HL) CB56 (W) - BIT bit 2 in (HL) CB5E (W) - BIT bit 3 in (HL) CB66 (W) - BIT bit 4 in (HL) CB6E (W) - BIT bit 5 in (HL) CB76 (W) - BIT bit 6 in (HL) CB7E (W) - BIT bit 7 in (HL) CB46 (W) - BIT bit 8 in (HL) FDCB + $Displacement + 4E (W+B+B) - BIT bit 1 in (IY + $) FDCB + $Displacement + 56 (W+B+B) - BIT bit 2 in (IY + $) FDCB + $Displacement + 5E (W+B+B) - BIT bit 3 in (IY + $) FDCB + $Displacement + 66 (W+B+B) - BIT bit 4 in (IY + $) FDCB + $Displacement + 6E (W+B+B) - BIT bit 5 in (IY + $) FDCB + $Displacement + 76 (W+B+B) - BIT bit 6 in (IY + $) FDCB + $Displacement + 7E (W+B+B) - BIT bit 7 in (IY + $) FDCB + $Displacement + 46 (W+B+B) - BIT bit 8 in (IY + $) DDCB + $Displacement + 4E (W+B+B) - BIT bit 1 in (IX + $) DDCB + $Displacement + 56 (W+B+B) - BIT bit 2 in (IX + $) DDCB + $Displacement + 5E (W+B+B) - BIT bit 3 in (IX + $) DDCB + $Displacement + 66 (W+B+B) - BIT bit 4 in (IX + $) DDCB + $Displacement + 6E (W+B+B) - BIT bit 5 in (IX + $) DDCB + $Displacement + 76 (W+B+B) - BIT bit 6 in (IX + $) DDCB + $Displacement + 7E (W+B+B) - BIT bit 7 in (IX + $) DDCB + $Displacement + 46 (W+B+B) - BIT bit 8 in (IX + $) 2F (B) - CPL A ;contents of the A are inverted ED44 (B) - NEG A ;contents of the A are negated 76 (B) - HALT ;executes NOPs until a subsequent interrupt or reset is received